A. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and, in particular, to a semiconductor integrated circuit which drives the addressing of a display device.
B. Description of the Related Art
Integrated circuits (IC) which control the addressing of Plasma Display Panels (PDP) include PDP address driver ICs. PDP address driver ICs generally have a high operational voltage of 50 volts or more, an instantaneous current of 5 amps or more, and a large consumption current of 300 mA or more, and comprise a multiplicity of 100 or more output bit portions.
Recently, in order to miniaturize PDP address driver ICs that comprise a multiplicity of output bit portions, semi-slim-type PDP address driver ICs have been developed (for an example, see T. Nomiyama, K. Kawamura, A. Fukuchi, K. Sato, Y. Shigeta, and G. Tada, “New 256-ch PDP Address Driver IC with Reducing Switching Noise” Proc. of International Display Workshop/Asia Display (IDW/AD'05), pages 453 to 456(2005)). See FIG. 5 for an example of a layout for a semi-slim type PDP address driver IC. FIG. 5 is a principal part view illustrating the layout of a PDP address driver IC which affords a planar view of the PDP address driver IC as seen from above.
The PDP address driver IC 200 comprises amplifier circuit section 201 at the center thereof and has a plurality of external connection terminals arranged at both ends thereof. Taking first edge 202 as an example, input terminal 203, as well as high voltage ground terminal 204 and high voltage power terminal 205 are disposed at the center of edge 202. Furthermore, high voltage ground terminal 204 and high voltage power terminal 205 are connected to high voltage ground wiring 206 and high voltage power wiring 207 respectively, and high voltage ground wiring 206 and high voltage power wiring 207 are arranged so as to extend within the plane of PDP address driver IC 200.
Incidentally, PDP address driver IC 200 actually has a postero-anterior orientation in FIG. 5 and is formed by metal wiring in a laminated structure (a multi-layered wiring structure), high voltage ground wiring 206 and high voltage power wiring 207 being pattern-formed on the uppermost layer of PDP address driver IC 200. For instance, if the laminated structure is a three layer structure, high voltage ground wiring 206 and high voltage power wiring 207 are positioned in the third layer, and wiring such as the signal wiring (not shown) from the logic circuit, and the wiring connected to the output terminal of the high-withstand voltage circuit (not shown) are laid in a complicated arrangement in the layer below the third layer.
Moreover, in the layer below high voltage ground wiring 206 and high voltage power wiring 207, output bit portions 208 are arranged without a gap in a linear manner in the range indicated by arrow C. A signal that enters through input terminal 203, which is formed in the third wiring layer, passes through amplifier circuit section 201, and after going through signal processing in an internal circuit, is transmitted to output bit portion 208, where it is output from output terminal 209, which is formed in the third wiring layer. This signal then designates an address of the panel (not shown).
In the same manner, for the semi-slim type PDP address driver IC 200 shown in FIG. 5, in order to miniaturize the PDP address driver IC, output bit portions 208 are arranged without a gap in a linear manner on both sides of PDP address driver IC 200. Further, high voltage ground wiring 206 is formed in the layer above all of output bit portions 208.
Next, the constitution of output bit portion 208 will be described. FIG. 6 provides principal part views illustrating the constitution of the output bit portions, where FIG. 6A is a layout diagram of the output bit portions and FIG. 6B is a constitutional view of the circuit of an output bit portion.
As shown in FIG. 6A, for output bit portions 208, the high-withstand voltage circuit section that outputs a signal to the panel is disposed in the region indicated by arrow D, and the logic circuit section that controls the high-withstand voltage circuit section is disposed as a set in the region indicated by arrow E. The above-mentioned high voltage ground wiring 206 and high voltage power wiring 207 are then arranged in the layer above the high withstand voltage circuit. Further, though it is not shown in FIG. 5, logic ground wiring 210 that supplies a ground potential to the logic circuit section is laid in the layer above the logic circuit section. Further, logic power source wiring 211 that supplies a predetermined voltage to the logic circuit section is also laid here.
As shown in FIG. 6B, the high-withstand voltage circuit section is constituted comprising a level shifter circuit that is constituted by active elements P1, P2, N1, and N2, as well as an output circuit that is constituted by active elements P3 and N3. Here, the level shifter circuit is a circuit that receives a signal from the logic circuit section and converts this signal into a high voltage signal. The output circuit outputs either the source potential or the ground potential, depending on the signal from the logic circuit section. Thus, output bit portions 208 comprise a high-withstand voltage section and a logic circuit section, and are arranged without a gap, in a linear manner, at both ends of PDP address driver IC 200 in the longitudinal direction thereof.
In recent years, there has been a trend towards reducing the number of PDP address driver ICs on each PDP module in order to reduce the overall cost of the PDP module. When the number of PDP address driver ICs on each PDP module is reduced, it is necessary to increase the number of output bit portions of each PDP address driver IC in order to maintain the output performance of each PDP module. For example, currently, PDP modules predominantly each have 256 output bit portions, but the next-generation PDP modules are tending to move towards having 384 or more output bit portions.
However, if the number of output bit portions provided in an individual PDP address driver IC is increased, the permitted current capacity of the metal wiring laid within the PDP address driver IC must be increased because the consumption current inside the PDP address driver IC increases. In other words, it is necessary to increase the line width of high voltage ground wiring 206 and high voltage power wiring 207 in order to increase the permitted current capacity. However, if we simply increase the width of the metal wiring in proportion to the increase in the number of output bit portions, problems such as the following arise.
FIG. 7 is a principal part view illustrating how the disposition of wires of greater width relates to the disposition of the output bit portions. As shown in FIG. 7, high voltage power wiring 213 is disposed outside the region directly above the high-withstand voltage circuit section.
Specifically, if the consumption current of the PDP address driver IC is set at 400 mA, in cases where the current capacity of the metal wiring with respect to width is 2 (mA/μm), high voltage ground wiring 212 and high voltage power wiring 213 would both have to have a metal wiring thickness of 200 μm to correspond to this current capacity. For example, if the region in which the high-withstand voltage circuit section is disposed is 350 μm wide, high voltage power wiring 213 is then placed more than 50 μm from the region directly above the region of the high-withstand voltage circuit section. In other words, high voltage power wiring 213 is then placed over a region in which no active elements are formed.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.